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ISL6131, ISL6132
Data Sheet July 22, 2005 FN9119.3
Multiple Voltage Supervisory ICs
The ISL6131 and ISL6132 are a family of high accuracy multi voltage supervisory ICs designed to monitor voltages greater than 0.7V in applications ranging from microprocessors to industrial power systems. The ISL6131 is an undervoltage four supply supervisor whereas the ISL6132 is a two voltage supervisor monitoring both for undervoltage (UV) and overvoltage (OV) conditions. Both ICs feature four external resistor programmable voltage monitoring (VMON) inputs each with a related STATUS output that individually reports the related monitor input condition. In addition there is a PGOOD (power good) signal that asserts high when the STATUS outputs are in their correct state. There is a stability delay of approximately 160ms to ensure that the monitored supply is stable before STATUS and PGOOD are released to go high. The PGOOD and STATUS outputs are open-drain to allow ORing of the signals and interfacing to a wide range of logic levels. STATUS and PGOOD outputs are guaranteed to be valid with IC bias lower than 1V eliminating concern about STATUS and PGOOD outputs during IC bias up and down. VMON inputs are designed to ignore momentary transients on the monitored supplies.
Features
* Operates from 1.5V to 5.5V Supply Voltage * Four Adjustable Voltage Monitoring Thresholds * 150ms STATUS/PGOOD Stability Time Delay * Four Individual Open Drain STATUS Outputs * Guaranteed STATUS/PGOOD Valid to VDD <1V * VDD and VMON Glitch Immunity * VDD Lock Out * 4mm X 4mm QFN Package * QFN Package: - Compliant to JEDEC PUB95 MO-220 QFN - Quad Flat No Leads - Package Outline - Near Chip Scale Package footprint, which improves PCB efficiency and has a thinner profile * Pb-Free Plus Anneal Available (RoHS Compliant)
Applications
* Multivoltage DSPs and Processors * P Voltage Monitoring * Embedded Control Systems * Graphics Cards * Intelligent Instruments
Ordering Information
PART NUMBER ISL6131IR ISL6132IR ISL6131IRZA (Note) ISL6132IRZA (Note) TEMP. RANGE (C) -40 to +85 -40 to +85 -40 to +85 -40 to +85 PACKAGE 24 Ld 4x4 QFN 24 Ld 4x4 QFN 24 Ld 4x4 QFN (Pb-free) 24 Ld 4x4 QFN (Pb-free) PKG. DWG. # L24.4x4 L24.4x4 L24.4x4 L24.4x4
* Medical Equipment * Network Routers * Portable Battery-Powered Equipment * Set-Top Boxes * Telecommunications Systems
ISL613XSUPEREVAL2 Evaluation Platform Add "-T" suffix for tape and reel. NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
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CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2003, 2004, 2005. All Rights Reserved All other trademarks mentioned are the property of their respective owners.
ISL6131, ISL6132
UVSTATUS_1
OVSTATUS_1
UVSTATUS_2
STATUS D
STATUS C
STATUS B
STATUS A
OVSTATUS_2
V2 IN
D IN
C IN
B IN
A IN
V1 IN Ru Rm Rl
VDD GROUND
VDD GROUND PGOOD1 PGOOD2 EN1 EN2
VMON_A VMON_B VMON_C VMON_D
UVMON_1 UVMON_2 OVMON_1 OVMON_2
PGOOD
EN
FIGURE 1. ISL6131 TYPICAL APPLICATION USAGE
FIGURE 2. ISL6132 TYPICAL APPLICATION USAGE
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FN9119.3 July 22, 2005
ISL6131, ISL6132 Pinout
ISL6131, ISL6132 (24 LD QFN) TOP VIEW
24 1 2 3 4 5 6 7 8 9 10 11 12 23 22 21 20 19 18 17 16 15 14 13
Pin Descriptions
PIN 6131 23 10 20 12 17 14 NA NA NA NA 24 6132 23 10 NA NA NA NA 12 20 17 14 24 PIN NAME VDD GND VMON_A VMON_B VMON_C VMON_D OVMON_1 UVMON_1 UVMON_2 OVMON_2 PGOOD On the ISL6131, PGOOD is the boolean AND function of all four STATUS outputs. On the ISL6132, PGOOD is for the AB pair and signals high when the monitored voltage is within the specified window and the A and B STATUS output states are correct. This is an open drain output and is to be pulled high to the appropriate level with an external resistor to a VDD maximum level. PGOOD2 is for the CD pair and signals high when the monitored voltage is within the specified window and when the C and D STATUS output states are correct. This is an open drain output and is to be pulled high to the appropriate level with an external resistor to a VDD maximum level. On the ISL6131 each STATUS provides a high signal through pull-up resistors about 160ms after its related VMON has continuously been > Vuv_vth. This delay is for stabilization of monitored voltages. STATUS will deassert and pull low upon VMON not being satisfied for about 30s. On the ISL6132 the STATUS outputs indicate compliance with a high output state for each pair of monitors. Bias IC from nominal 1.5V to 5V IC ground On the ISL6131 these inputs provide for a programmable UV threshold referenced to an internal 0.633V. The related STATUS output will assert once the related input > internal reference voltage. On the ISL6132, these inputs provide for a programmable UV and OV threshold referenced to an internal 0.633V reference. In the `AB' pair VMON_A is the UV input and VMON_B is the OV input. In the `CD' pair VMON_C is the UV input and VMON_D is the OV input. These inputs have a 30s glitch filter to prevent PGOOD reset due to a transient. FUNCTION DESCRIPTION
NA
9
PGOOD2
2 5 6 7 NA NA NA NA 1 NA NC
NA NA NA NA 5 2 6 7 1 11
STATUS_A STATUS_B STATUS_C STATUS_D OVSTATUS_1 UVSTATUS_1 UVSTATUS_2 OVSTATUS_2 EN1 EN2
On ISL6131 provides 4 voltage UV function enabling/disabling input. Internally pulled up to VDD. Controls monitor 1 (AB pair) on ISL6132. On ISL6132, controls monitor 2 (CD pair) voltage, voltage monitoring function enabling input, pulled up to VDD. No Connect
3, 4, 8, 13, 15, 16, 18, 19, 21, 22
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FN9119.3 July 22, 2005
ISL6131, ISL6132
Absolute Maximum Ratings
VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +6.0V VMON, ENABLE, STATUS, PGOOD . . . . . . . . . . -0.3V to VDD+0.3V ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2kV (HBM)
Thermal Information
Thermal Resistance (Typical, Notes 1, 2) JA (C/W) JC (C/W) 4x4 QFN Package . . . . . . . . . . . . . . . . 48 9 Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150C Maximum Storage Temperature Range . . . . . . . . . . . -65C to 150C Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300C (QFN - Leads Only)
Operating Conditions
VDD Supply Voltage Range . . . . . . . . . . . . . . . . . . . . +1.5V to +5.5V Temperature Range (TA) . . . . . . . . . . . . . . . . . . . . . . .-40C to 85C
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES: 1. JA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details. 2. For JC, the "case temp" location is the center of the exposed metal pad on the package underside. 3. All voltages are relative to GND, unless otherwise specified.
Electrical Specifications
PARAMETER VMON/ENABLE INPUTS VMON Threshold VMON Threshold Temp. Coeff. VMON Hysteresis VMON Glitch Filter VMON Minimum Input Impedance
Nominal VDD = 1.5V to +5V, TA = TJ = -40C - 85C, Unless Otherwise Specified SYMBOL TEST CONDITIONS MIN TYP MAX UNIT
VVMONvth TCVMONvth VVMONhys Tfil Zin_min
TJ = 25C TJ from -40C to +85C
619 -
633 40 10 30 8
647 -
mV nV/C mV s M
Tj = 40C, VMON within 63mV of VVMONvth VMON valid, EN high to STATUS & PG high EN low to PGOOD low EN low to STATUS low EN open -
ENABLE L2H, Delay to STATUS & PGOOD EN H2L, Delay to PGOOD EN H2L, Delay to STATUS ENABLE Pull-up Voltage ENABLE Threshold Voltage STATUS/PGOOD OUTPUTS STATUS Pull-Down Current STATUS/PGOOD Delay after VMON Valid STATUS/PGOOD Output Low BIAS IC Supply Current IC Supply Current IC Supply Current VDD Power On VDD Power On Lock Out IVDD_5.5V IVDD_3.3V IVDD_1.5V VDD_POR VDD_LO IRSTpd TdelST Vol VENVTH
160 13 VDD VDD/2
0.1 -
ms s s V V
RST = 0.1V VMON > VUVvth to STATUS = 0.2V Measured at VDD = 1.0V
-
88 160 0.04
0.1
mA ms V
VDD = 5V VDD = 3.3V VDD = 1.5V VDD high to low VDD low to high
-
170 145 100 0.89 0.91
1 -
A A A V V
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FN9119.3 July 22, 2005
ISL6131, ISL6132 Description and Operation
The ISL6131 is a four voltage high accuracy supervisory IC designed to monitor multiple voltages greater than 0.7V relative to PIN 10 of the IC. Upon VDD bias power up, the STATUS and PGOOD outputs are held correctly low once VDD is as low as 1V. Once biased to 1.5V the IC continuously monitors from one to four voltages independently through external resistor dividers comparing each voltage monitoring (VMON) pin voltage to an internal 0.633V (VVMONvth) reference. With the EN input driven high or open as each VMON input rises above VVMONvth a timer is set to ensure ~160ms of continuous compliance then the related STATUS output is released to be pulled high. The STATUS outputs are opendrain to allow ORing of these signals and interfacing to a logic high level up to VDD. The STATUS are designed to reject short transients (~30s) on the VMON inputs. Once all STATUS outputs are high a power good (PGOOD) output signal is generated high to indicate all the monitored voltages are greater than minimum compliance level. Once any VMON input falls below VVMONvth for longer than the glitch filter time both the PGOOD and the related STATUS output are pulled low. The other STATUS outputs will remain high as long as their corresponding VMON voltage remains valid and the PGOOD validation process is reset. Figure 1 illustrates ISL6131 typical application schematic and Figure 3 is an operational timing diagram. See Figures 10 to 17 for ISL6131 function and performance. Figures 10 and 11 show the VDD rising along with STATUS and PGOOD response. Figures 12 and 13 illustrate VMON falling below VVMONvth and Figure 14 illustrates VMON rising above VVMONvth with STATUS and PGOOD response. Figure 15 shows the VDD failing with STATUS and PGOOD response. Figures 16 and 17 illustrate ENABLE to STATUS and PGOOD timing. If less than four voltages are being monitored, connect the unused VMON pins to VDD for proper operation. All unused STATUS outputs can be left open. The ISL6132 is a dual voltage monitor for under and overvoltage compliance. Figure 2 illustrates the typical ISL6132 implementation schematic and Figure 4 is the operational timing diagram. There are 2 pairs of monitors each with an undervoltage (UVMON) input and overvoltage (OVMON) input along with with associated STATUS and PGOOD outputs. Upon VDD bias power up, the STATUS and PGOOD outputs are held correctly low once VDD is as low as 1V. Once biased to 1.5V the IC continuously monitors the voltage through external resistor dividers comparing each VMON pin voltage to an internal 0.633V reference. At proper bias the OVSTATUS are pulled high and the UVSTATUS and PGOOD are pulled low. Once the UVMON input > the VMON Vth continuously for ~160ms, its associated STATUS output will release high indicating that the minimum voltage condition has been met. As both UVMON and OVMON inputs are satisfied the PGOOD output is released to go high indicating that the monitored voltage is within the specified window. Figure 18 illustrates this performance for a 4V to 5V window. When VMON does not satisfy its voltage high or low criteria for more than the glitch filter time, the associated STATUS and PGOOD are pulled low. Figures 19 and 20 illustrate this performance for a 4V to 5V compliant window. Figures 21-23 illustrate the VMON glitch filter timing to STATUS and PGOOD notification and transient immunity. The ENABLE input when pulled low allows for monitoring and reporting function to be disabled. Figure 24 shows ENABLE high to PGOOD timing for compliant voltage. When choosing resistors for the divider remember to keep the current through the string bounded by power loss tolerance at the top end and noise immunity at the bottom end. For most applications total divider resistance in the 10k -100k range is advisable with 1% tolerance resistors being used to reduce monitoring error. Referencing Figures 1 and 2, choosing the two resistor values is straightforward for the ISL6131 as the ratio of resistance should equal the ratio of the desired trip voltage to the internal reference, 0.633V). For the ISL6131, two dividers of two resistors each can be employed to monitor the OV and UV levels for each voltage. Otherwise, use a single three resistor string for each voltage. In the three resistor divider string the ratio of the desired over voltage trip point to the internal reference is equal to the ratio of the two upper resistors to the lowest (gnd connected) resistor. The desired under voltage trip point ratio to the internal reference voltage is equal to the ratio of the uppermost (voltage connected) resistor to the lower two resistors. An example follows; 1. Establish lower and upper trip level: 3.3V 20% or 2.64V (UV) and 3.96V (OV) 2. Establish total resistor string value: 10k, Ir = divider current 3. (Rm+Rl)*Ir = 0.623V @ UV and Rl * Ir = 0.633V @ OV 4. Rm+Rl = 0.623V / Ir @ UV => Rm+Rl = 0.623V / (2.64V /10k) = 2.359k 5. Rl = 0.633V / Ir @ OV => Rl = 0.633V /(3.96V/10k) = 1.598k 6. Rm = 2.359k - 1.598k = 0.761k 7. Ru = 10k - 2.397k = 7.641k 8. Choose standard value resistors that most closely approximate these ideal values. Choosing a different total divider resistance value may yield a more ideal ratio with available resistors values.
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FN9119.3 July 22, 2005
ISL6131, ISL6132
A B C D D C
VMONVth VMON INPUT VOLTAGE
STSDLY STSDLY STSDLY
STSDLY
>Tfil STSDLY
STATUS OUTPUTS
A
B
C
D
C
PGOOD OUTPUT EN INPUT
FIGURE 3. ISL6131 OPERATIONAL DIAGRAM
OVERVOLTAGE LIMIT UNDERVOLTAGE LIMIT
OV Tfil MONITORED VOLTAGE RAMPING UP & DOWN OVSTATUS
UVSTATUS
PGOOD OUTPUT
FIGURE 4. ISL6132 OPERATIONAL DIAGRAM
Typical Performance Curves
634 633 VB BIAS CURRENT (mA) 80 100 UV THRESHOLD (mV) 632 631 630 629 628 627 626 -40 VDD = 1.5V VDD = 5V 0.30 0.25
0.20 0.15 0.1 0.05
-20
0
20
40
60
-40
-20
0
20
40
60
80
100
TEMPERATURE (C)
TEMPERATURE (C)
FIGURE 5. UV THRESHOLD
FIGURE 6. VDD CURRENT
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FN9119.3 July 22, 2005
ISL6131, ISL6132 Applications Usage
Using the ISL613XSUPEREVAL2 Platform
The ISL613XSUPEREVAL2 platform is the primary evaluation board for this family of supervisors and is designed to support the ISL6131, ISL6132. In addition, it also supports the ISL6125 sequencer as it has open drain RESET# outputs similar to the STATUS outputs of the ISL6131 and ISL6132. The ISL613XSUPEREVAL2 is shipped with a ISL6125 soldered into the SMD channel 2 position and with 2 each of the ISL6131 (1 socketed) and ISL6132 loose packed. The four resistor divider strings are set so that VMON = VMON Vth (0.633V) once supplies are 2.10V on the IN_D, 1.27V on IN_C, 4.27V on IN_B and 2.78V on IN_A. On the ISL6131 these are the 4 UV levels at ~85% of 2.5V, 1.5V, 5V and 3.3V respectively. LEDs turned off are the PGOOD high indicators with D4 being the ISL6131 indicator. With VDD ranging from 1.5V to 5V or shorted to IN_A through JP1 and with an ISL6131 in the socket, PGOOD will release to be pulled high once those minimum conditions are met. See Figures 10 to 17 for performance and function examples. With the ISL6132 in the socket and IN_C and IN_D tied to a common supply and IN_A and IN_B tied to a second supply the ISL6132 will look for a voltage between 1.27V to 2.10V on the CD pair and between 2.78V and 4.27V for the AB pair. Once either supply meets its requirement the related PGOOD will release to pull high and turn off the related LED. See Figures 18 to 24 for performance and function examples. Figures 25 and 26 illustrate the ISL613XSUPEREVAL2 platform in image and schematic. on. Additional ISL6131s can be employed in parallel to sequence any number of DC-DC convertors is in this fashion.
VIN EN VIN EN VIN EN
VOUT DC-DC_A VOUT DC-DC_B
VOUT DC-DC_C
ABC STATUS PGOOD
VMON_A VMON_D
ISL6131 VMON_C
VDD ENABLE VMON_B GND
FIGURE 7. ISL6131 `LOSSLESS' SEQUENCING CONFIGURATION
Using the ISL6131 for System Voltage and Over Temperature Monitoring
Being a multivoltage monitoring IC the ISL6131 can also be used to monitor over temperature as well as voltage for a more complete coverage of system health. Using a Negative Temperature Coefficient (NTC) passive device in place of one of the resistors in a VMON divider provides over temperature monitoring either locally or remotely. Evaluations of this application configuration have involved the QT0805T-202J, QT0805Y-502J and QT0805Y-103J NTCs from Quality Thermistor. ISL6131 over temperature monitoring is not as accurate as specific temperature monitor ICs but this implementation provides a cost efficient solution with 5% tolerances achievable. See Figures 8 - 9 for over temp sensing configuration and operation results. In this example, the desired maximum temp is 100C. The QT0805Y-103J NTC was placed at the end of 3 feet of twisted pair wire to emulate a remote sensing application. From the Quality Thermistor data sheet, this NTC device has a +25C value of 10K and at +100C a value of 0.923K. An accompanying standard value resistor of 3.83K was chosen for divider so that at 100C, VMON ~0.633V with the bias voltage at 3.3V.
Using the ISL6131, ISL6132 for Negative Voltage Monitoring Applications
The ISL6131, ISL6132 can be used for -V monitoring as it monitors any voltage more positive relative to its GND pin. With correct bias differential these parts can monitor any voltage regardless of polarity or amplitude.
Using the ISL6131 for `Loss Less' Sequencing Applications
The ISL6131 can be used in a `loss less' sequencing application where a monitored output voltage determines the start of the next sequenced turn-on. As shown in Figure 7, VMON_A input looks at the common VIn of several DC-DC converters and enables DC-DC_A with STATUS _A, once both VIn and ENABLE are satisfied. VMON_B monitors the output of DC-DC_A and when the acceptable output voltage is reached, DC-DC_B is enabled with STATUS_B output. This sequencing pattern is continued until all DC-DC outputs are on, at which time PGOOD signal will be released to indicate. 160ms delay from VMON > VVMONVth to STATUS high ensures stability at each step prior to subsequent turn7
FN9119.3 July 22, 2005
ISL6131, ISL6132
The resulting falling VMON trip point with configuration shown is ~0.634V, with ~0.642V for rising which equates to ~95C for under temperature and ~97C for over temperature respectively. Choosing the standard resistor value above and below R1 allows for small adjustments in the temperature trip point. The low ISL6131 VMON temperature coefficient makes this a viable and low cost addition to complete system monitoring.
TEMP (C) 25 50 75 95 100 105 VMON (V) 2.36 1.61 1.01 0.67 0.61 0.54 TEMP STATUS H = Under Temp H = Under Temp H = Under Temp H = Under Temp L = Over Temp L = Over Temp
TEMP INDICATOR 3.3V 3.83k R1
STATUS VDD
VMON 0.1V/DIV
VMON T QT0805Y-103J (REMOTE HEAT SOURCE LOCATION)
ISL6131
GND Low = OVER TEMP
TEMP STATUS 5V/DIV
10s/DIV
FIGURE 8. ISL6131 OVER TEMP SENSING CONFIGURATION
FIGURE 9. ISL6132 OVER TEMP SENSING RESULT
Functional and Performance Waveforms
VDD RISING
STATUS OUTPUTS PULLED-UP TO 1.5V
STATUS OUTPUTS TO VDD VDD RISING PGOOD
PGOOD
1V/DIV
100s/DIV
1V/DIV
200s/DIV
FIGURE 10. ISL6131 VDD RISING
FIGURE 11. ISL6131 VDD RISING WITH PULL-UP
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FN9119.3 July 22, 2005
ISL6131, ISL6132 Functional and Performance Waveforms (Continued)
VMON FALLING BELOW UV Vth (0.1V/DIV) UV Vth 0.63V UNRELATED STATUS OUTPUTS VMON FALLING BELOW UV Vth (0.1V/DIV) UV Vth 0.63V
UNRELATED STATUS OUTPUTS
RELATED STATUS OUTPUT RELATED STATUS OUTPUT PGOOD PGOOD
1V/DIV
40ms/DIV
1V/DIV
10ms/DIV
FIGURE 12. ISL6131 VMON FALLING TO PGOOD
FIGURE 13. ISL6131 VMON FALLING TO PGOOD
VMON RISING ABOVE UV Vth (0.1V/DIV) UV Vth 0.63V
UNRELATED STATUS OUTPUTS
VDD FALLING
STATUS OUTPUTS
RELATED STATUS OUTPUT
PGOOD
PGOOD
1V/DIV
20ms/DIV
1V/DIV
40ms/DIV
FIGURE 14. ISL6131 UV RISING TO PGOOD
FIGURE 15. ISL6131 VDD FALLING
ENABLE ENABLE STATUS STATUS
PGOOD PGOOD
2V/DIV
20ms/DIV
2V/DIV
2s/DIV
FIGURE 16. ISL6131 ENABLE L2H TO PGOOD
FIGURE 17. ISL6131 EN H2L TO PGOOD
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FN9119.3 July 22, 2005
ISL6131, ISL6132 Functional and Performance Waveforms (Continued)
MONITORING 4V TO 5V MONITORING 4V TO 5V OV STATUS
VDD RISING MONITORED VOLTAGE FALLING UV/PGOOD STATUS RISING
OV STATUS RISING
PGOOD AND UV STATUS PULLED LOW
1V/DIV
40ms/DIV
1V/DIV
10ms/DIV
FIGURE 18. ISL6132 TURN-ON
FIGURE 19. ISL6132 IN UV CONDITION
MONITORING 4V TO 5V
MONITORING 4V TO 5V
UV STATUS MONITORED VOLTAGE RISING
VMON FALLING (1V/DIV)
4V MIN LIMIT
UV STATUS PGOOD AND OV STATUS PULLED LOW OV STATUS
PGOOD 1V/DIV 10ms/DIV 5V/DIV 10s/DIV
FIGURE 20. ISL6132 IN OV CONDITION
FIGURE 21. ISL6132 UV GLITCH FILTER TIMING
MONITORING 4V TO 5V
VMON RISING (1V/DIV)
5V MAX LIMIT
VMON 5.5V TO 3.5V UV STATUS UV, OV STATUS & PGOOD 5VOUT
OV STATUS
PGOOD 5V/DIV 10s/DIV 8s/DIV
FIGURE 22. ISL6132 OV GLITCH FILTER TIMING
FIGURE 23. ISL6132 GLITCH FILTER TRANSIENT IMMUNITY
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FN9119.3 July 22, 2005
ISL6131, ISL6132 Functional and Performance Waveforms (Continued)
ENABLE PGOOD
OV, UV STATUS
1V/DIV
20ms/DIV
FIGURE 24. ISL6132 ENABLE TO PGOOD
FIGURE 25. ISL613XSUPEREVAL2 PHOTOGRAPH
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FN9119.3 July 22, 2005
ISL6131, ISL6132
VDD JP1 IN4 IN3 R17 IN1 R18 R15 R16
IN2
1 R1 R3 R5 R7
2
3 STATUS
4
VDD VMON2 (OV1) R2 R4 R6 R8 VMON4 (OV2) VMON3 (UV2) VMON1 (UV1) ISL6131, ISL6132 PGOOD1 PGOOD2 D4 C1 R9 R10 D3
GND EN1 EN2
FIGURE 26. ISL613XSUPEREVAL2 CHANNEL 1 SCHEMATIC
TABLE 1. ISL6131SUPEREVAL2 BOARD CHANNEL 1 COMPONENT LISTING COMPONENT DESIGNATOR DUT1 DUT2 R1A R2A R7A R8A R3A R4A R5A R6A R15-R18 C1A D3, D4 COMPONENT FUNCTION ISL6131, Quad Under Voltage Supervisor in socket ISL6132, Dual Over & Under Voltage Supervisor in bag IN2 to VMONB (OV1) Resistor for Divider String VMONB (OV1) to GND Resistor for Divider String IN1 to VMONA (UV1) Resistor for Divider String VMONA (UV1) to GND Resistor for Divider String IN4 to VMOND (OV2) Resistor for Divider String VMOND (OV2) to GND Resistor for Divider String IN3 to VMONC (UV2) Resistor for Divider String VMONC (UV2) to GND Resistor for Divider String STATUS Pull-up Resistors Decoupling Capacitor PGOOD# INDICATOR COMPONENT DESCRIPTION Intersil, ISL6131IR Quad Under Voltage Supervisor Intersil, ISL6132IR Dual Over & Under Voltage Supervisor 8.45k 1%, 0402 1.47k 1%, 0402 7.68k 1%, 0402 2.26k 1%, 0402 6.98k 1%, 0402 3.01k 1%, 0402 4.99k 1%, 0402 4.99k 1%, 0402 5.1k 10%, 0402 0.1F, 0805 SMD RED LED
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FN9119.3 July 22, 2005
ISL6131, ISL6132 Quad Flat No-Lead Plastic Package (QFN) Micro Lead Frame Plastic Package (MLFP)
L24.4x4
24 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE (COMPLIANT TO JEDEC MO-220VGGD-2 ISSUE C) MILLIMETERS SYMBOL A A1 A2 A3 b D D1 D2 E E1 E2 e k L L1 N Nd Ne P 0.25 0.30 1.95 1.95 0.18 MIN 0.80 NOMINAL 0.90 0.20 REF 0.23 4.00 BSC 3.75 BSC 2.10 4.00 BSC 3.75 BSC 2.10 0.50 BSC 0.40 24 6 6 0.60 12 0.50 0.15 2.25 2.25 0.30 MAX 1.00 0.05 1.00 NOTES 9 9 5, 8 9 7, 8 9 7, 8 8 10 2 3 3 9 9 Rev. 2 10/02 NOTES: 1. Dimensioning and tolerancing conform to ASME Y14.5-1994. 2. N is the number of terminals. 3. Nd and Ne refer to the number of terminals on each D and E. 4. All dimensions are in millimeters. Angles are in degrees. 5. Dimension b applies to the metallized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. 6. The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1 identifier may be either a mold or mark feature. 7. Dimensions D2 and E2 are for the exposed pads which provide improved electrical and thermal performance. 8. Nominal dimensions are provided to assist with PCB Land Pattern Design efforts, see Intersil Technical Brief TB389. 9. Features and dimensions A2, A3, D1, E1, P & are present when Anvil singulation method is used and not present for saw singulation. 10. Depending on the method of lead termination at the edge of the package, a maximum 0.15mm pull back (L1) maybe present. L minus L1 to be equal to or greater than 0.3mm.
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com 13
FN9119.3 July 22, 2005

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